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Over the last decade, Monte Carlo simulations have emerged as the most useful way of predicting the yield of RSFQ circuits, as they consider all manufacturing tolerance effects on a circuit, and are not restricted to bias current variations. Here we finally present a comprehensive definition of layout-extracted Monte Carlo model creation for lumped-element Spice simulations-from the local and global values for inductance, resistance and junction area from statistical models, to the inclusion of parasitics, layer-to-layer variations, variations in the penetration depth, and capacitance and mutual coupling. Finally, the addition of bias current trimming to the simulations to compensate for most global variations is described, and comparative yield results listed.
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Fourie et al. (2005) studied this question.
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