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A new superconducting logic family, complementary output switching logic (COSL), is proposed. The family consists of AND, NAND, OR, NOR, and XOR gates. The performance of the gates is predicted with a procedure that evaluates the dynamic performance when all circuit parameters are randomly varied around the nominal values. The simulated performance of the gates is compared with modified variable threshold logic (MVTL) at 5 GHz and 10 GHz. The functionality and margins of the COSL gates are verified by measurements at low speed.
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Perold et al. (1996) studied this question.
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