Chip-Scale Modeling of Electroplated Copper Surface Profiles

In this paper, a methodology for the characterization and modeling of pattern-dependent problems in copper interconnect topography is presented. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semiempirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, linewidth distributions, and line length are extracted for each cell in a 40 × 40 μm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 Å for array height and around 500 Å for step height. This methodology provides the first known chip-scale prediction of electroplated topography.