Bias–stress-induced threshold voltage shift dependence of negative charge trapping in the amorphous indium tin zinc oxide thin-film transistors

Indium tin zinc oxide (ITZO)-based thin-film transistors (TFTs) were fabricated by dc magnetron sputtering in Ar + O2 reactive gas, at room temperature. We present the effect of post-deposition annealing of ITZO thin films on the oxygen vacancies and on the characteristics of TFT devices. When the annealing temperature was increased from room temperature to 350 °C, the resistivity of ITZO film increased from 2.05 × 101 to 2.60 × 103 Ω cm and the interface trap density (Nt) of the TFTs reduced from 3.18 × 1013 to 4.83 × 1011 cm−2. The TFT with the ITZO film which was annealed at 350 °C showed a very small shift in turn-on voltage, even after applying positive bias stress of +12 V for 104 s. The current–voltage characteristics of 350 °C annealing temperature sample indicated that these TFTs were in an enhanced mode of transistor operation with a high on-to-off current ratio of ∼1.26 × 106, high field-effect mobility of 14.17 cm2 V−1 s−1, and low subthreshold slope of 1.23 V/dec. The trapping time reduced from 3720 to 1546 s as the annealing temperature increased from room temperature to 350 °C. These results suggest that thermal annealing played an important role in reducing defects as well as improvement in stability of the TFTs.