An analytic Iarge-signal model for the GaAs FET is described which relates the terminal currents to the instantaneous terminal voltages and their time derivatives. It incorporates the device geometry and semiconductor parameters as well as the device parasitic circuit elements. The model is fast and efficient when implemented on a computer and is in a form suitable for large-signal circuit design and optimization.
No takes yet. Share an insight, caveat, or question.
Madjar et al. (1981) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: