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A technique for vertically interconnecting two conducting layers separated by an insulater is described. The technique offers advantages over present methods, including complete step coverage over vertical via walls and a planarized surface. In addition, this technique can be extended easily to form multiconductor‐insulator interconnects. Moreover, as device dimensions are reduced to the micron and submicron level, the planarization and therefore the interconnection will improve. The method will have applications in integrated electronics and perhaps integrated optics and other semiconductor devices.
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Sirkin et al. (1984) studied this question.
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