A 60-GHz CMOS VCO Using Capacitance-Splitting and Gate–Drain Impedance-Balancing Techniques

The design and measurement of a 60-GHz 90-nm CMOS voltage-controlled oscillator is presented. To reduce the power consumption and to improve the phase-noise performance, a capacitance-splitting and a gate-drain impedance-balancing techniques, which are realized with an inductive divider, are proposed. With these techniques, the size of the cross-coupled pair is reduced. Analysis of the proposed techniques shows that the transistorg mgeneration efficiency is improved and the oscillator noise factor is reduced. Moreover, the tank loaded quality factor is increased by balancing impedance levels across the transistor terminals. The 60-GHz oscillator was fabricated in a 90-nm CMOS technology. Under 0.6-V supply, the oscillator achieved a tuning range from 61.1 to 66.7 GHz, consuming only 3.16 mW. At 64 GHz, the phase noise is -95 dBc/Hz at 1-MHz offset.