Low Power Architecture for Asip’s: Based on Adiabatic Switching Principles

Power minimization is one of the primary concerns in today VLSI design methodologies because of two main reasons one is the long battery operating life requirement of mobile and portable devices and furthermore, the number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. In this paper a low power architecture for ASIP is proposed. Proposed architecture is designed using adiabatic switching principles. Proposed adiabatic ASIP is tested using VHDL. The results show that performance of adiabatic ASIP is better than other contemporary ASIPs