Design of ultra‐low power AES encryption cores with silicon demonstration in SOTB CMOS process

The design of ultra‐low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2‐Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1‐Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent.