A Computational Model to Predict Material Removal Depth in Wire-Edm of Silicon Wafers Slicing

Wire-electrical discharge machining (wire-EDM) has the potential to manufacture ultra-thin silicon wafers, significantly enhancing the efficiency of solar photovoltaic cells. However, the fabrication of ultra-thin silicon (Si) wafers through wire-EDM is constrained by its inherently lower material removal rate. This limitation can potentially reduce the throughput rate of solar cell production. The key to producing wafers with the maximum material removal rate lies in selecting the optimal processing parameters. The traditional experimental-based optimization is time-consuming and complex. To address this, a computational model of the wire-EDM process is developed. This model aims to predict the material removal depth and identify the best process parameters. The approach involves solving the heat diffusion equation, taking into account the heating caused by the surface heat flux. The finite element method is used to solve the model equations and evaluate material removal depth by analyzing the simulated temperature profiles. The simulation results indicate that the open voltage significantly influences the material removal depth, compared to pulse on-time. According to the computational model, the calculated material removal depth is 2.5µm when using 74 V and 0.5 µs pulse on-time. The study emphasizes the importance of using computational modeling to understand the effect of open voltage and pulse-on time on material removal depth during the wire-EDM process, as it provides valuable insights without experiments. By identifying the material removal depth, this research contributes to enhancing the efficiency of producing ultra-thin silicon wafers for solar cell manufacturing.