Hardware Efficient Majority Gate Based Approximate Multipliers

Approximate computing has become a well-known technology in recent times. It is one of the promising hardware architectures with its advantages. However, there is a huge gap in the advancement of battery technology and hardware, the approximation technique has come into the limelight over the recent years. This paper proposes approximate multiplier designs that make use of novel logic circuitry majority logic function and the input-reordering circuit. Majority logic is a major building block that is widely used in digital electronics, as well as an input re-ordering circuit (IROC) that aids in the reduction of hardware circuitry and cell area. The proposed multipliers result in significant improvement in terms of total area, power dissipation, and timing delay as compared to the exact accurate designs and are also applied to the image processing application to evaluate the hardware metrics such as Mean Error Distance, Relative Mean Error Distance and Peak Signal to Noise Ratio. 45-nm CMOS standard cells are used to synthesize the proposed architectures. The results proved the efficiency of the proposed architectures.