Radix rᵏ FFTs: Matricial Representation and SDC/SDF Pipeline Implementation

This paper proposes to use the discrete Fourier transform (DFT) matrix factorization based on the Kronecker product to express the family of radixrksingle-path delay commutator/single-path delay feedback (SDC/SDF) pipeline fast Fourier transform (FFT) architectures. The matricial expressions of the radixr,r2,r3, andr4decimation-in-frequency (DIF) SDC/SDF pipeline architectures are derived. These expressions can be written using a small set of operators, resulting in a compact representation of the algorithms. The derived expressions are general in terms ofrand the number of points of the FFTN. Expressions are given where it is not necessary thatNis a power ofrk. The proposed set of operators can be mapped to equivalent hardware circuits. Thus, the designer can easily go from the matricial representations to their implementations and vice versa. As an example, the mapping of the operators is shown for radix 2, 22, 23, and 24, and the details of the corresponding SDC/SDF pipeline FFT architectures are presented. Furthermore, a general expression is given for the SDC/SDF radixrkpipeline architectures whenk> 4. This general expression helps the designer to efficiently handle a wider design exploration space and select the optimum single-path architecture for a given value ofN.