A high-resolution time interpolator based on a delay locked loop and an RC delay line

An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology.