A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis

This paper proposes an ultra-compact 4 to 10-Gb/s 5-tap current-mode transmitter to realize the sub 1-TiI fractional de-emphasis (DE) using a hybrid delay line, which is alternatively controlled by the voltage bias and clock. It exhibits the scalability between the clocked 0.5-TiI and 1-TiI DEs and data rate. The sub-1-TiI DE provides wide tunability of the data amplitude and delay to compensate different channel losses between the 1stand 2ndNyquist frequencies while effectively compensating the high-frequency portion of the pseudo-random binary sequence (PRBS) spectrum for data jitter improvement. Additional techniques are a two-step current-summing scheme, namely, two-step DE in the data path, and active inductors in both the data and clock paths to enhance the internal bandwidth without the need for passive inductors. In addition, we present an analytical model for predicting data-dependent jitter (DDJ) based on a generic system's step response, derive the exact closed-form DDJ expression of DE, and verify its validity by mean of circuit simulation. Prototyped in 65-nm CMOS technology, it achieves a figure-of-merit of 4.6 mW/Gb/s and an output jitter of 10.8 psppat 10 Gb/s under a PRBS 231-1 pattern. The data eyes measure 0.62-TiI-horizontal and 19.5%-vertical openings after -20-dB channel loss. The die area is 0.0071 mm2.