Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme

This paper presents the design and analysis of a serial link transceiver (TRX) architecture employing analog multi-tone signaling for chip-to-chip communication. Multi-tone single-sideband signaling scheme is proposed in TRX architecture in order to optimize bandwidth requirements for each sub-channel and to improve signal-to-noise ratio by reducing inter-channel interferences (ICI) between neighboring sub-channels. System-level modeling results show that the proposed TRX architecture enables equalizer-free communication at 16 Gb/s over a lossy backplane channel that exhibits 22-dB attenuation at 8 GHz, while conventional non-return-to-zero signaling TRX necessitates a two-stage continuous-time linear equalizer. A channel frequency-response inversion scheme, the up/down-conversion mechanism of the TX/RX data stream and the RX design considerations have been analyzed and investigated by architectural modeling.