In this paper, the partial gate recess for performance improvement of enhancement-mode (E-mode) GaN power devices is experimentally demonstrated. The gate recess with a careful control of the recess depth was performed with an optimized recessed barrier thickness of ~1.5 nm that is thin enough to completely deplete the 2-D electron gas channel in the gate region. Meanwhile, the remaining barrier preserves the as-grown quantum well of the heterostructure physically intact and thus, effectively mitigates the lattice damage caused by gate recess. The fabricated E-mode Al2O3/AlGaN/GaN MISFETs deliver a threshold voltage (VTH) of +1.5 V. The maximum drain current density (ID,max) and transconductance (Gm,max) are 693 mA/mm and 166 mS/mm, respectively. The MISFETs with an LGDof 10 μm feature an OFF-state breakdown voltage of 860 V at a leakage current of 1 μA/mm. The corresponding specific ON-resistance (RON,sp) is as low as 1.18 mΩ·cm2yielding a high-power figure of merit of 626 MW/cm2. In comparison with the reference MOSFETs by fully gate recess, the respectably improved device performance of the MISFETs attributes to the enhanced electron mobility achieved by the partial gate recess.
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Zhou et al. (2015) studied this question.
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