Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors

The full width at half maximum (FWHM) of the negative differential conductance (NDC) characteristics in room temperature (RT)-operating silicon single-hole transistors (SHTs) has been studied by experiments and calculations. It is found that when the voltage gain of the SHT is higher, sharper NDC and smaller FWHM are achieved. Lower drain coupling is considered to be the main reason for the small FWHM in a resonant tunneling system of RT-operating SHTs. FWHM of NDC of as small as 95mV has been obtained in a SHT with the gain of as high as 5.2 at RT, which is the highest value of the gain ever reported. The device is in the form of an ultranarrow wire channel metal oxide semiconductor field-effect transistor, which shows large Coulomb blockade oscillations at RT and has extremely small drain capacitance due to its ultranarrow channel structure. NDC can now be designed by device parameters, showing further potential for application to low-voltage, low-power NDC circuits.