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Wireless neural-recording instruments eliminate the bulky cables in multi-channel signal transmission, while the system size should be reduced to mitigate the impact on freely-moving animals. As the battery usually dominates the system size, the neural-recording chip should be low power to minimize the battery in long-termly monitoring. In general, a neural-recording chip consists of an analog front end (AFE) and an 8 bit$-$10 bit analog-to-digital converter (ADC), while it's challenging to design an ADC with an 8$-$10 effective number of bits (ENOB) and sub-μW power consumption due to the kickback noise. In this work, we propose a kickback-reduction technique for a successive-approximation-register (SAR) ADC based on neural-recording chip. Fabricated in 65 nm CMOS process, the proposed technique reduce the ADC power to 315 nW, resulting in an 8-channel neural-recording chip with 249μW in total. Measured results show that the chip achieves an ADC ENOB of 9.73 bits, as well as an AFE gain of 43.3 dB and input-referred noise (IRN) of 9.68μ Vᵣₘₛin a bandwidth of 0.9 Hz$-$7.2 kHz. Combined with a BLE chip and a PCB antenna, the chip is implemented into a 2.6 g wireless headstage system (w/o battery), and anin-vivodemonstration is conducted on a male Sprague-Dawley rat with Parkinson's disease. The headstage system transfers thein-vivoneural signals to a commodity smartphone through BLE, and the miniature size induces little impact on freely-moving activities.
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Zhang et al. (2022) studied this question.
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