We report on an 8-bit successive approximation analog-to-digital converter (SA-ADC) that was designed and fabricated in 0.5-mum silicon on sapphire CMOS technology. The SA-ADC is capable of 32-MHz operation, providing 1.23-MS/s conversion rates, and consumes 800 muW at 3.3-V supply. The lack of substrate parasitic capacitances enables the use of small-area capacitors and reduces the noise coupling to the analog nodes. The circuits employ MOS transistors of different thresholds to optimize the performance and power dissipation of the system
No takes yet. Share an insight, caveat, or question.
Culurciello et al. (2006) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: