Grain Size and Temperature Dependence of the Electrical Behaviour of Polysilicon

The effect of grain size (D) and temperature (T) on the electrical behaviour of polysilicon is investigated theoretically by considering a simplified carrier trapping model and an empirical expression for grain boundary trapping states density. The model presented applies well for all grain sizes over the entire range of doping concentration and temperature. The computed variations of electrical properties, such as resistivity and mobility, with D and T are seen to be in agreement with the experimental findings. It is observed that the effect of temperature is more pronounced for smaller grain sizes whereas for larger values of D the properties tend to those of a single crystal.