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Wide-bandgap semiconductor devices are widely used in power electronic systems for their high switching speed and frequency characteristics, which enhance power density and output fidelity, but also cause serious common-mode (CM) electromagnetic interference (EMI) issues. Balance technique is a promising method due to its significant CM noise suppression ability and high-power density. However, conventional balance techniques are typically constructed with additional inductors and front input grounding parasitic capacitors, which the high-frequency impedance of the former is affected by the equivalent parallel capacitances while the latter is sensitive to variations of front input circuits. To solve the aforementioned issues, an improved balance technique considering input parasitic inductor is proposed in this article. First, the CM EMI model and propagation paths of a dc–ac converter are analyzed. Second, a Wheatstone bridge is constructed with input parasitic inductor. Then, additional capacitors are introduced to achieve the balance condition. Furthermore, the effect of parasitic parameters of the additional CM current path on the CM reduction performance is investigated. Finally, the effectiveness of the proposed method is verified through simulation and experiments.
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Qing et al. (2024) studied this question.
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