Improvement of Performance Deviation and Productivity of MOSFETs With Gate Length Below 30 nm by Flash Lamp Annealing

The impact of new flash lamp annealing (FLA) technology, which both minimizes diffusion to yield a shallow junction and realizes low sheet resistivity, is investigated based on MOSFET fabrication and computer simulations. Productivity can be improved since FLA makes it possible to employ higher acceleration energy ion implantation and higher throughput. The MOSFET performance can be improved and its deviation suppressed by using FLA. In analyzing MOSFETs with gate length (L) of 20 nm by computer simulations, it was clarified that in contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of |I/sub off/| with a low channel surface dopant concentration. This provided a higher mobility value and a higher drive current. FLA is promising for improving the performance and productivity of sub-30-nm gate-length MOSFETs.