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Selective area ion implantation doping has been used to fabricate GaN junction field effect transistors (JFETs). p-type and n-type doping was achieved with Ca and Si implantation, respectively, followed by a 1150 °C rapid thermal anneal. A refractory W gate contact was employed that allows the p-gate region to be self-aligned to the gate contact. A gate turn-on voltage of 1.84 V at 1 mA/mm of gate current was achieved. For a ∼1.7 μm×50 μm JFET with a −6 V threshold voltage, a maximum transconductance of 7 mS/mm at VGS=− 2V and saturation current of 33 mA/mm at VGS=0 V were measured. These results were limited by excess access resistance and can be expected to be improved with optimized n+ implants in the source and drain regions.
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Zolper et al. (1996) studied this question.
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