A Ka-band three-stage CMOS power amplifier was designed and fabricated using 0.18 mum gate-length common-source transistors. For low loss and accurate matching networks for the amplifier, a substrate-shielded microstrip-line was used with good modeling accuracy up to 40 GHz. The measured insertion loss was 0.5 dB/mm at 25 GHz. The three-stage amplifier achieved a 14.5 dB small-signal gain, 14 dBm output power, and 13.2% power-added-efficiency at 27 GHz in a compact chip area of 0.84 mm2. The measured gain was the highest for Ka-band power amplifiers using common-source transistors. These results were achieved at a voltage compatible with deep sub-micrometer CMOS technology.
No takes yet. Share an insight, caveat, or question.
Lee et al. (2008) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: