Dry etching of amorphous-Si gates for deep sub-100 nm silicon-on-insulator complementary metal–oxide semiconductor

Sub-100 nm gates are fabricated for fully depleted silicon-on-insulator complementary metal–oxide semiconductor transistor and circuit fabrication using optical lithography and a high density, transformer coupled plasma etch process. The antireflective coating (ARC) bake temperature and HBr/Cl2/O2 organic ARC etch chemistry were optimized to maintain device critical dimension. The amorphous silicon (a-Si) main etch uses HBr/Cl2/He/O2 and was optimized at a high HBr concentration, high temperature, low O2 concentration, and a low pressure to obtain minimal CD bias and maximum selectivity to both oxide and resist. Main Etch end-point determination was developed to trigger on a rising Cl2 reactant optical emission signature at 510 nm avoiding interference from CO lines at typical end-point determination wavelengths for integration using resist masks with a high percentage of resist area. Transistors were fabricated with gate lengths of 25 and 50 nm.