AI-Native Semiconductor Engineering: Reinforcement Learning, Graph Neural Networks, and Digital Twins as Core Design Infrastructure

At sub-5 nm process nodes, traditional semiconductor scaling is coming up against physical and economic limits, with Moore's Law no longer applicable. At the same time, the need for computation power is increasing and growing every day with the advent of Artificial Intelligence (AI), 5G/6G communications and autonomous systems. In this survey paper, we suggest that the semiconductor design industry is in a structural shift to an AI native paradigm, where reinforcement learning (RL), graph neural networks (GNNs), digital twins, and agentic orchestration frameworks are key and not auxiliary parts of the chip design flow. This paper: (i) reviews the physical, economic and workforce pressures driving the transition; (ii) summarizes the results of a survey of demonstrated work in RL for floor planning and placement, GNN for EDA prediction and digital-twin enabled pre-fabrication validation; (iii) categorizes placement methodologies and their evaluation protocols; (iv) presents a detailed technical decomposition of each AI-native pillar; (v) analyses the economic case for investing in AI-native design; (vi) discusses open research challenges and four tractable directions along which this research will progress; and (vii) suggests a roadmap for a four-stage curriculum for preparing the next-generation semiconductor engineer. The analysis shows that learned placement methods can be competitive with, but do not yet consistently outperform, well-designed classical placement algorithms, confirming that the need for well-designed classical placement algorithms remains crucial as AI-native tools approach production use.