Suppression of the boron penetration induced dielectric degradation by using a stacked-amorphous-silicon film as the gate structure for pMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p/sup +/ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO/sub 2/ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950/spl deg/C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO/sub 2/ interface of the p/sup +/ SAS gate capacitor is much smoother than that of the p/sup +/ SAS gate capacitor.