Investigation of Threshold Voltage Variability at High Temperature Using Takeuchi Plot

The property of metal–oxide–semiconductor field-effect transistors' (MOSFETs) threshold voltage (V T) variability at high temperature is investigated by evaluating the device matrix array test element group (DMA-TEG). It is revealed that V T variation is lower at high temperature than at room temperature, and that V T at high temperature has a strong correlation with V T at room temperature. The normal property of V T variability both at room and high temperatures is validated using the normal probability plot. The decrease in V T variation at high temperature stems from the reduction of the channel depletion layer width (W dep). The temperature dependence of V T variation is evaluated using the Takeuchi plot, the V T variation normalization method. It is revealed that the change in B VT, the parameter of V T variation in the Takeuchi plot, is very small with varying temperature.