Single-Layer 8-Element Planar Quasi-Yagi Array With Co-Designed Balun, Parasitic-Loop Decoupler, and T-Junction/Delay-Line Feed for 28-GHz 5G FR2

A single-layer 8-element planar quasi-Yagi linear array is presented for 28-GHz 5G FR2 (n261) applications. The integrated microstrip-to-slotline balun, the parasitic-loop LC decoupler, and the 1-to-8 T-junction/delay-line power-divider network are co-designed on a single Rogers RT/Duroid 5880 substrate with matched reference planes and a via-free, coplanar realization, so that the three blocks share one ground and one set of line widths instead of being laid out on three independent boards. The three building blocks are individually verified in Ansys HFSS and then assembled and re-tuned as a single structure: (i) a microstrip-to-slotline balun with a shorted-stub impedance-transformation network; (ii) a parasitic-loop LC band-stop decoupler that pulls inter-port coupling below −25 dB at half-wavelength spacing; and (iii) a planar 1-to-8 corporate divider in two variants — an in-phase T-junction for broadside, and a 45° delay-line variant producing −120° per-stage progressive phase for θ = + 41.8∘ passive steering. In HFSS the stand-alone in-phase and delay-line dividers exhibit ≤ 0.3 / 0.4-dB amplitude imbalance, ≤ 5 / 7° phase imbalance, and ≥ 15 -dB return loss across n261. The fully integrated, passive array prototypes measure 12.3–13.1 dBi (broadside) and 11.7–12.5 dBi (+41.8°) of realized gain, H-plane side-lobe levels ≤ -10 dB (T-junction) and ≤ -9 dB (delay-line), and inter-element isolation ≤ -23 dB over the full n261 band. Element-level HFSS simulations with an ideal external phase shifter indicate an upper-bound ±55° scan envelope with ≤ 2.3 -dB scan loss; this simulated ceiling is not realized by the passive prototypes. The result is a via-free, low-profile, low-cost path to high-gain mmWave front-ends for 5G terminals.