Scalable PD/SOI CMOS with floating bodies

An insightful analysis of the floating-body (FB) effect on off-state current (I/sub off/) in PD/SOI MOSFETs is done based on simulations calibrated to a published scaled SOI CMOS technology (Chau et al., 1997). In contrast to the conclusion drawn by Chau, the simulations reveal that proven, easily integrated processes for enhancing carrier recombination in the source/drain junction region, in conjunction with the normal elevated chip temperature of operation, can effectively suppress the FB-induced increase of I/sub off/, thus enabling exploitation of the unique benefits of scaled PD/SOI CMOS circuits.