State creation and hole trapping in polycrystalline silicon thin film transistors at high drain bias

Drain current walk-out and on-current degradation have been seen for n-channel polycrystalline silicon thin film transistors stressed at high drain biases. The drain current walk-out is attributed to the slow trapping of hot holes in the gate oxide, and the on-current degradation to the creation of fast interface acceptor states in the upper half of the band gap. Both effects are at least in part removed by annealing at 100 degrees C. No positive threshold shifting is seen on stressing, even though a high density of electron traps is known to exist in the oxide. It thus seems likely that the acceptor states are created by injected holes rather than electrons. In view of the fact that both state creation and trapping effects occur and anneal simultaneously, it is proposed that hot carrier injection form a continuous distribution of states from the interface inwards, and the associated continuum of trapping time constants gives rise to the fast- and slow-trapping phenomena observed.