True background calibration technique for pipelinedADC

A digital background calibration technique for a pipelined analogue-to-digital converter (ADC) is presented. The calibration technique involves the use of a slow, but accurate, ADC in conjunction with a least-mean squares (LMS) algorithm to find the parameters, which correct for residue errors such as finite op-amp gain error, capacitor ratio mismatch and charge injection error in a non-ideal pipeline stage, resulting in a significant improvement in the INL and the DNL of the ADC.