Two-Dimensional Mapping of pn Junctions by Electron Holography

We demonstrate two-dimensional mapping of pn junctions in transistors by electron holography. The source and drain areas in phase images of 0.3 μm CMOS transistors can be delineated with the correct sign of the potential change, thus enabling a distinction between NMOS and PMOS devices in TEM holography. Measurements of samples containing abrupt boron marker layers establish a spatial resolution of 5 nm for mapping the electrostatic potential distribution across pn junctions.