Development methodology for high-κ gate dielectrics on III–V semiconductors: GdxGa0.4−xO0.6∕Ga2O3 dielectric stacks on GaAs

A three step methodology for the development of gate dielectrics on III–V semiconductors including atomistic interface studies, oxide template formation, and dielectric stack manufacturing has been proposed. The third and final step encompasses the realization of high-κ GdxGa0.4−xO0.6∕Ga2O3 dielectric stacks on GaAs. This article reports high-κ stacked gate oxides with an oxide relative dielectric constant of 20.8±1, a breakdown field exceeding 4MV∕cm, leakage currents of ≅2×10−8A∕cm2 at an electric field of 1MV∕cm, and a broad minimum of interface state density Dit⩽2×1011cm−2eV−1 on n-type GaAs suggesting a U-shaped Dit distribution. The proposed methodology can potentially be extended to high-κ gate dielectric development on elemental semiconductors such as Si and Ge and wide band gap semiconductors such as GaN.