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A method for the analysis of lossy distributed interconnections on high-speed LSI/VLSI chips is presented. The method is based on a piecewise decomposition technique in which nonlinear branches are replaced by piecewise-linear time-dependent sources. Parameters of the piecewise-linear functions are computed iteratively so that the network's topological and constitutive relations are satisfied. Examples to illustrate the analysis algorithms are presented.
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M. Nakhla (1990) studied this question.
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