Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages

A novel four-quadrant CMOS analog multiplier has been designed and integrated using linearized differential stages as basic building blocks. The multiplier offers high input resistance and linear input ranges of /spl plusmn/2.5 V for a supply voltage of /spl plusmn/5 V. A 3-dB bandwidth of at least 1.6 MHz is attainable for either input.