Porous Low-k Impacts on Performance of Advanced LSI Devices with GHz Operations

The impact of porous low- k films on circuit performance in GHz operation was investigated using high-speed circuits in 65 nm complementary metal oxide semiconductor (CMOS) LSI with 11-layered Cu dual damascene interconnects (DDIs). By introducing new non-porogen-type porous films, such as molecular-pore-stacking (MPS) SiOCH films, local low- k /Cu structures (M2–M5) with effective dielectric constants ( K eff ) of 3.1 and 2.9 were fabricated, and their circuit performances were compared to those with conventional local interconnects with K eff =3.4. The interline capacitance ( C int ), measured using an LCR meter at ∼100 kHz, was reduced by 12% from K eff =3.4 to 2.9. NAND-type ring oscillators (ROSCs), which were designed to have ∼1.5 GHz oscillation, also achieved 12 and 10% reductions in signal delay and power consumption, respectively. A 2 GHz static random access memory (SRAM) with K eff =2.9 provides a 4% reduction in bit-line capacitance (M2), resulting in a 6% decrease in V ddmin , or eventually widening the SRAM operation margin. The porous low- k impact on GHz operation is demonstrated for the first time.