Characteristics of an integrated spiral inductor with an underlying n-well

Effects due to presence of n-wells with bias and no bias under spiral inductors are described. Inductors with underlying n-wells are fabricated using a 0.8-/spl mu/m CMOS process. S-parameters are measured at different n-well bias conditions and equivalent circuit parameters are extracted and compared. The results show that when the n-well-to-substrate junctions are reverse biased parasitic capacitance associated with the inductors can be reduced approximately by a factor of 2 and the peak quality factor (Q) can be increased by /spl sim/10%. This reduction in the parasitic capacitance should enable widening of the inductor metal traces to increase the Q at low frequencies while keeping the parasitic capacitance and self-resonance frequency constant.