Design and implementation of a turbo decoder for 3G W-CDMA systems

This paper presents the design and hardware implementation of a log-MAP turbo decoder used in the third generation (3G) mobile communication W-CDMA systems. The decoding algorithm is highly data dominated and needs many memories for data storing. The memory requirements are systematically investigated and optimized from two aspects: (1) an alternative called state metric difference-storing method is proposed to save the forward state metric (/spl alpha/) and the backward state metric (/spl beta/) memory up to 1/3; (2) the interleaver address memory is reduced by repeating the address calculation at each iteration. The experimental results on an FPGA prototype of the decoder show that it supports 2Mbits/s data rate with five iterations, and for code blocks of more than 2000, a bit error rate (BER) of 10/sup -6/-10/sup -7/ is achieved at E/sub b//N/sub o/=1.0 dB after only five iterations.