An experimental high speed 1:4 demultiplexer integrated circuit featuring output bit alignment, reduced gate count, and a novel circuit architecture is presented. The experimental circuit features an inherently fast two-stage configuration, with operation at up to 30 Gbit/s demonstrated in an advanced AlGaAs/GaAs heterojunction bipolar technology. The system clock frequency is half the bit rate with only one additional self-generated internal clock necessary.
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Runge et al. (1997) studied this question.
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