Bipolar transistor scaling laws indicate that the dissipated power per unit collector-junction area increases in proportion to the square of the transistor bandwidth, increasing to /spl sim/10/sup 6/ W/cm/sup 2/ for InP heterojunction bipolar transistors (HBTs) designed for 160 Gb/s operation. A verified three-dimensional finite-element thermal model has been used to analyze the thermal resistance of InP in the context of 80 and 160 Gb/sup -1/ integrated circuits. The simulations show that the maximum temperature in the device can be significantly higher than the experimentally determined base-emitter junction temperature. Devices suitable for 160-Gb/s circuits will be thermally possible if the InGaAs etch-stop or contacting layer is removed from the subcollector.
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Harrison et al. (2004) studied this question.
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