Design and implementation of a CMOS K-winners-take-all circuit are presented. The proposed architecture is of O(n) complexity and enables the number of winners to be determined before each competition phase by adjusting the current ratio of two current sources. A 10-cell test chip has been designed and fabricated in a 3 /spl mu/m CMOS process. Functionality has been verified by testing. The simple structure of the circuit is highly suitable for analog VLSI implementations.
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Sekerkiran et al. (1999) studied this question.
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