A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications

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In this article, a low-power and energy-efficient hybrid full adder circuit is proposed, which is implemented based on multi-threshold NAND and NOR gates and transmission gate multiplexers. In order to implement this circuit, carbon nano tube field effect transistors are utilised. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects power, delay and power-delay product. The results are presented and displayed the superiority of the proposed cell in different voltage levels, load conditions, temperatures and robustness against process variations.