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In this paper, a method to fabricate Silicon-on-Nothing (SON) MOSFETs using H + and He + co-implantation is presented. The technique is compatible with conventional CMOS technology and its feasibility has been experimentally demonstrated. SON MOSFETs with 50nm gate length have been fabricated. Compared with the corresponding bulk MOSFETs, the SON MOSFETs show higher on current, reduced leakage current and lower subthreshold slope.
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Wei-Hai et al. (2006) studied this question.
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