Scaling capability improvement of silicon-on-void (SOV) MOSFET

In this paper, the scaling capability improvement of silicon-on-void (SOV) MOSFET is comprehensively investigated. The results show that SOV MOSFET shows a significant improvement in the suppression of the short-channel effects (SCE) caused by the potential coupling between the source and drain through the buried layer. In addition, the parasitic capacitance between the source/drain and the substrate can be greatly decreased. The minimal channel length of SOV MOSFET is reduced by 27% compared with ultra-thin-body (UTB) SOI MOSFET. Most of all, the limitation of silicon film thickness of SOV MOSFET can be relaxed to about 50%, in comparison with SOI MOSFET. SOV MOSFET can alleviate the critical problem and further improve the immunity of SCE of UTB SOI MOSFET in the nanoscale regime. SOV MOSFET will be a good choice of device structure to put off the eventual limit in scaling down.