Space Vector Techniques for a Binary-Cascaded Multilevel Inverter Operating Under Reduced Common-Mode Voltage With Reduced Commutations

This paper presents a novel space vector pulse width modulation (SVPWM) for a three-phase binary cascaded multilevel inverter. The SVPWM could become impractical in multilevel inverters (MLIs) because of its increasing complexity with a larger number of levels. Theghcoordinate system can ease the digital implementation, but to generate the inverter'sabcstates from the nearest three vectors (NTVs), iterative computations are required every sampling instant. This paper proposes further reduction of computations by directly generating theabcstate with minimum common-mode voltage (CMV) from aghvector. Subsequently, only one vector among the NTVs is required for implementing the proposed SVPWM. The reduced CMV profile within the NTVs further permits the reduction of commutations by clamping one phase during a sampling period. The presented technique exhibits full dc bus utilization capability and can be implemented in the binary cascaded MLI (BCMLI) and further applied to anyM-level MLI. Also, ifMis considerably large or if switching losses and electromagnetic interference emissions must be minimized, nearest vector modulation with reduced CMV along with line-frequency operation of high-voltage cells can be implemented to reduce the switching losses. Experiment results of a BCMLI is presented to verify the effectiveness of the proposed technique.