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Insulating CdS layers are formed on conducting CdS crystals by diffusion of copper. The layers are 1–10 μm thick and have resistivity of 108 Ω·cm. The layer thickness as determined from capacitance measurements does not depend on the applied voltage. Current-voltage curves have Ohmic and square-law regions in fields below 104 V/cm, and thereafter, they rise very steeply (j∝V5). Breakdown occurs at average fields of 5×105 V/cm. Pulsing to 105 V/cm greatly reduces the low-field resistance, frequently increasing the capacitance; this is shown to be due to a peripheral expansion of the diffused layer together with a formation of breakdown channels. Field-controlled freeing of carriers from traps is indicated by the rise of current with time at voltages above threshold, while below threshold the current pulse is decaying, due to trapping. Observations made along and perpendicular to c axis are similar.
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Simhony et al. (1968) studied this question.
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