Practical considerations for analog operation of bucket-brigade circuits

The bucket-brigade circuit offers a means of implementing a clock-controlled analog delay line in monolithic form. Operating in the sampled-data domain, it combines some of the advantages of both analog and digital circuits and appears to have a strong application potential in analog signal processing systems. In this paper, the analog operation of bucket-brigade circuits is described with respect to such practical operating considerations as bandwidth, dynamic range, linearity, power dissipation, baseband, signal recovery, a clock waveform noise. Experimental results from p-channel MOSFET and n-channel JFET brigades are presented.