In the standard MOSFET description of the drain currentI_Das a function of applied gate voltageV_ GS, the subthreshold swingSS(T)≡ dV_GS/ dlog I_ Dhas a fundamental lower limit as a function of temperatureTgiven bySS(T)=ln 10\,\, k_ B T/ e. However, recent low-temperature studies of different advanced CMOS technologies have reportedSS(4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation ofSS(T)in 28 nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4 K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying the Fermi–Dirac statistics. This results in a subthresholdI_ D~ e^ eV_GS/ k_ B T₀forT₀=35K with saturation valueSS( T< T₀)= ln 10\,\, k_ B T₀/ e. The proposed model adequately describes the experimental data ofSS(T)from 300 down to 4 K usingk_ B T₀ 3meV for the width of the exponential tail and can also accurately describeSS( I_ D)within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and the design of cryogenic circuits.
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Bohuslavskyi et al. (2019) studied this question.
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