A defect relaxation model for bias instabilities in metal-oxide-semiconductor capacitors

We have studied electron trapping and detrapping resulting from bias stress applied to a metal-sputtered oxide-native oxide-semiconductor capacitor. The trapping process is described as band-to-trap tunneling. Based on the assumption of a trap with a delta function spatial distribution, a model was developed that predicts a trap energy distribution and defect relaxation energy. Application of this model to experimental data reveals a value for the relaxation energy of approximately 1 eV. We suggest that this model may apply to hysteretic instabilities observed in p-channel transistors and dual dielectric memory devices.